Field of the Invention
The invention relates to a circuit for generating a signal with adjustable frequency. In particular, the invention is intended for generating a radiofrequency signal, as is required for example in radio transmission apparatuses, cordless telephones, mobile telephones and other transmission apparatuses and systems. The possibility, afforded by the invention, of adjusting the frequency of the generated signal can be used for example for the purpose of frequency and/or phase modulation of the generated signal. Furthermore, the generated signal may serve as an (unmodulated) carrier signal whose frequency is kept stable with the aim of automatic frequency control independently of changing operating conditions (supply voltage, temperature, etc.).
It has been known heretofore to generate a signal with adjustable frequency by means of a digital synthesis circuit. Such a circuit, which is also referred to as a DDS circuit (DDS=direct digital synthesizing), is contained for example in the module with the type designation AD7008 available from Analog Devices.
That digital synthesis circuit has an accumulator, that is to say a clocked, storing summer with feedback whose counting range is swept through cyclically. The cycle duration depends on the clock frequency and on the magnitude of an applied additive value. The respective present counter reading of the accumulator is output to a look-up table, in order to generate data values which form a sine curve from the counting range that is swept through in sawtooth fashion. The data values generated by the look-up table are converted into an analog, sinusoidal output signal of the digital synthesis circuit by a digital/analog converter.
The output signal of a digital synthesis circuit of this type has relatively poor spectral purity, however. This is due to the fact that the resolution of the digital/analog converter is limited. Furthermore, the look-up table and the digital/analog converter require a high outlay on components, which is higher, the more stringent the requirements made of the signal quality. Finally, the digital/analog converter, in particular, has a relatively high current consumption and is poorly integrable, which is disadvantageous for use in battery-operated apparatuses, such as mobile telephones, for example.
U.S. Pat. No. 5,517,534 discloses, a PLL circuit, i.e., a circuit for generating a signal with adjustable frequency, with the following features: a reference oscillator generates a reference signal. A comparison signal device having an addition value input and a clock input generates a digital comparison signal, whose frequency depends on an addition value signal present at the addition value input and on a clock signal present at the clock input. A phase comparator generates a tuning signal depending on the result of a comparison of the phase of the reference signal with the phase of the comparison signal. An oscillator is driven by the tuning signal and generates the output signal and an oscillator signal, from which the clock signal present at the clock input of the comparison signal device can be derived. The comparison signal device has an accumulator clocked by the clock signal, and the comparison signal is derived from the counter reading of the accumulator. In other words, the pulse generator is clocked by the output signal of the PLL circuit (oscillator signal) and is enabled or inhibited depending on counter readings of a plurality of accumulators.
It has become known from the article "A Short Survey of Frequency Synthesizer Techniques" by V. Reinhardt et al. in Proceedings of the 40th Annual Frequency Control Symposium, Philadelphia, 1986, pages 355-65, to add a random number to the output signal of an accumulator in order to reduce the intensity of sidebands in the output spectrum of DDS circuits.
Additional information, in this context, may be gleaned from the German published patent application DE 196 53 022 A1 (not prior art). There is shown a frequency synthesizer in which overflow pulses of a digital accumulator are fed to a phase detector of a phase locked loop.